Those skilled in the art recognize that output buffers of metal oxide semiconductor (MOS) integrated circuits are susceptible to damage from electrostatic discharge (ESD). ESD events are typically conducted to the integrated circuit through the output bond pads which connect the integrated circuit to external package terminals. The integrated circuits may be exposed to ESD events before the packaging operation, but more typically are exposed to ESD events after packaging, such as during shipping or handling operations.
Those skilled in the art understand that when MOS devices are coupled between a bond pad an input to a circuit that experiences an ESD event, the MOS devices can operate as bipolar transistors in a snap-back mode. Moreover, conventional MOS device layouts often include multiple fingers of similar or identical devices, wherein each finger is associated with a commonly formed channel. When such MOS devices experience an ESD event, the snap-back operation is limited to the devices in only one of the fingers of similar MOS devices. Accordingly, the excessive charge on these MOS devices causes the devices to fail at an undesirably low stress level. Furthermore, the MOS devices of many conventional configurations are isolated from adjacent devices formed in the same finger, such that the ESD event is isolated to a limited number of devices along a single finger or channel. This isolation also creates non-uniformity of the ESD effect among all of the MOS devices, rendering those devices most affected more susceptible to failing at a low level of stress.
The design techniques used to protect output buffers from ESD include the use of output resistors and/or voltage clamping devices such as diodes or transistors. These devices serve to limit the maximum voltage that can appear at the drain electrode of one or more output transistors. Such conventional clamping devices are disclosed in U.S. Pat. Nos. 4,821,089, 4,806,999 and 4,990,802. However, these clamping devices do not provide an adequate amount of protection and can undesirably decrease switching rates. Moreover, the integration of the clamping devices requires additional processing steps and results in larger devices.
Another approach is disclosed in U.S. Pat. No. 5,838,033, which describes a resistor formed in the tub region adjacent the drain electrode. However, as with the clamping devices discussed above, this “diffused resistor” also requires additional processing steps and consumes additional surface area on the substrate.
Accordingly, what is needed in the art is a device and method of manufacture thereof that is easily integrated into existing processing procedures and that overcomes the above-described disadvantages of the prior art.